The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices.
During the scaling trend, various materials have been implemented for the gate electrode and gate dielectric for CMOS devices. There has been a desire to fabricate these devices with a metal material for the gate electrode and a high-k dielectric for the gate dielectric. An interfacial layer, such as an oxide layer, is typically formed between the high-k dielectric layer and the silicon substrate to facilitate formation of the high-k dielectric layer and improve electrical properties at the interface. However, problems have arisen when forming the interfacial layer such as poor wetting characteristics for high-k deposition and oxide re-growth during subsequent processing.
Accordingly, what is needed is a new and improved method for forming an interfacial layer and high-k dielectric layer on a substrate.